ADC0809 DATASHEET PDF

Once loaded the multiplexer sends the appropriate channel to the converter on the chip. The ALE should be pulsed for at least ns in order for the addresses to get loaded properly. As with all control signals it is required to have an input value of Vcc - 1. The following control signals are used to control the conversion. Clock The clock signal is required to cycle through the comparator stages to do the conversion. There are 8, 8 clock cycle periods required in order to complete an entire conversion.

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The heart of this single chip data acquisition system is its 8-bit analog-to-digital converter. The converter is designed to give fast, accurate, and repeatable conversions over a wide range of temperatures.

The converter is partitioned into 3 major sections: the R ladder network, the successive ap- proximation register, and the comparator. Monotonicity is particularly important in closed loop feedback control systems. A non-monotonic relationship can cause os- cillations that will be catastrophic for the system. Additionally, the R network does not cause load variations on the ref- erence voltage.

The bottom resistor and the top resistor of the ladder net- work in Figure 1 are not the same value as the remainder of the network.

The difference in these resistors causes the output characteristic to be symmetrical with the zero and full-scale points of the transfer curve. The successive approximation register SAR performs 8 it- erations to approximate the input voltage. For any SAR type converter, n-iterations are required for an n-bit converter.

Figure 2 shows a typical example of a 3-bit converter. The conversion is begun on the falling edge of the start conversion pulse. A conversion in process will be in- terrupted by receipt of a new start conversion pulse.

Con- tinuous conversion may be accomplished by tying the end-of-conversion EOC output to the SC input. If used in this mode, an external start conversion pulse should be ap- plied after power up. End-of-conversion will go low between 0 and 8 clock pulses after the rising edge of start conversion.

It is this section which is responsible for the ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the repeatability of the device. A chopper-stabilized comparator provides the most effective method of satisfying all the converter require- ments.

The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed through a high gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier since the drift is a DC component which is not passed by the AC am- plifier. Figure 4 shows a typical error curve for the ADC as measured using the procedures outlined in AN

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